Due to recent spread of CDs and DVDs, it is general for an individual person to record a large amount of information on an optical disk medium or reproduce information from the optical disk medium. Minute marks are recorded on the optical disc medium along with a guide groove of a spiral shape formed on the medium. This mark train is obtained by adding error correcting code to digital data including video information or music information, and recorded as 1-bit sequential information modulated by modulation codes.
During reproduction from an optical disc, the optical disc medium is rotated by a spindle motor, and the light emitted from a light source is focused using an objective lens, thereby irradiating a laser spot onto the medium surface. At this moment, a focus-direction actuator is controlled so that the distance between the objective lens and the medium surface is maintained constant, whereas another actuator is also controlled along a radial direction so that the laser spot correctly tracks the guide groove. The reflected light, i.e., laser beam irradiated onto and reflected from the medium surface changes between light and dark due to the presence or absence of the mark on the medium, and is converted by a photodetector into an electric signal (readout signal). Since the readout signal is weak, it is amplified by an amplifier, and subjected to a variety of filtering processings to improve the signal-to-noise ratio of the readout signal.
In order to convert the readout signal into the 1-bit digital information train, it is needed to extract from the readout signal a clock that is in synchrony with the readout signal. This is because a deviation of central axis etc. of the optical recording medium slightly deviates the channel rate of the readout signal even if the rotational speed of the spindle is correctly controlled, to thereby deviate the position to be identified if a fixed-frequency clock timing is employed. Extraction of the clock generally uses a PLL (phase locked loop) circuit. The 1-bit digital information train is obtained by binarizing and extracting the readout signal by using a specific threshold at the synchronized timing output from the PLL circuit. This information train is demodulated, and thereafter subjected to error correction etc. to finally provide the image and/or music information.
FIG. 8 shows the configuration of a typical PLL circuit. The PLL circuit 200 includes, as the basic configuration, three elements including a phase comparator (PC) 202, a loop filter (LPF) 203, and a voltage-controlled oscillator (VCO) 205. In the PLL circuit 200, the phase comparator 202 compares the phase difference between the input signal and an output of the VCO 205, the loop filter 203 removes harmonic components and noise component from the resultant signal of phase comparison, and a feed-back loop is formed wherein the output frequency of the VCO 205 is controlled based on the output from the loop filter 203. Thus, the operation is such that the output of VCO 205 synchronizes with the input signal.
Assuming that the transfer characteristics of the phase comparator 202, loop filter 203 and VCO 205 in the PLL circuit 200 are Kp, F(s) and Kv/s, respectively, the open-loop transfer characteristic G(s) is expressed by the following formula (1):G(s)=Kp·Kv·F (s)/s   (1)The closed-loop transfer characteristic H(s) thereof is expressed by the following formula (2):H(s)=G(s)/(1+G(s))   (2)If the G(s) is a first order, there is no frequency pull-in stage, whereby the pull-in range is narrow, and both the quick response and low jitter cannot be satisfied. For this reason, a secondary- or higher-order characteristic is employed. For example, if the F(s) is configured by an adder of an integrator and a first-order LPF, the F(s) is expressed by the following formula (3):F(s)=(ω0/s)+{1/(1+s/ω2)}  (3)Further, if Kp and Kv are combined so that:Kp·Kv=ω1   (4),the open-loop transfer characteristic is that shown by graph (i) in FIG. 9. The open-loop transfer characteristic assumes −12 dB/Oct. for an angular frequency of below or equal to ω0 and above or equal to ω2, and assumes −6 dB/Oct. for an angular frequency of ω0 to ω2. In FIG. 9, graph (ii) represents the LPF characteristic whereas graph (iii) represents the VCO characteristic. The response characteristic of the PLL loop is defined by the characteristic angular frequency shown by ω0, ω1 and ω2. A higher value for ω0 enables tracking of a lower-frequency frequency fluctuation with a reduced error; however, the clock litter increases on the contrary due to an increased noise frequency band that passes through the LPF.
In the mean time, since the optical recording medium is a low-price removable medium, the disk may be involved with a curvature, or may experience a deviation during the chucking thereof. This may sometimes cause the readout signal read from the disk to experience a fluctuation that is in synchrony with the spindle rotation and has a frequency component lower than the channel frequency. In order to reproduce information from such a readout signal, it is needed for the PLL circuit to raise the band of the loop characteristic to some degree, to thereby suppress the frequency fluctuation to a sufficient degree. However, the readout signal has a lower SNR, and if the band is excessively raised, jitter increases due to the noise on the contrary, thereby increasing the possibility of loss of synchronization. In particular, if the data is decoded from information that is recorded with a higher density, the loop characteristic of the PLL circuit used for data reproduction considerably affects the data decoding performance.
Control of disk rotation will be described hereinafter. Control of the disk rotation includes two main types of technique. More specifically there are a CLV (constant linear velocity) control technique that fixes the linear velocity, and a CAV (constant angular velocity) control technique that fixes the rotational angular velocity. Of these techniques, the CLV control is such that the spindle rotational speed is 2.4 times different between the inner periphery and the outer periphery, whereby there arises the problem that a significant waiting time is needed for the spindle control during a random access, and this waists a large amount of electric power. On the other hand, the CAV technique is such that the spindle is rotated at a constant speed, whereby a waiting time is not needed for the rotational speed to thereby improve the accessibility. For this reason, there is an increasing number of apparatuses using the CAV control technique.
During reproducing in a disk drive of the CAV control from a disk on which recording is performed by the CLV control, the synchronizing clock for the readout signal changes about 2.4 times between the inner periphery and the outer periphery, whereby a PLL circuit is needed that has a wide lock-in range and a capture range. On the other hand, the loop characteristic of a typical analog PLL is constant irrespective of the frequency of the input readout signal, due to the configuration of the analog circuit. Accordingly, if the PLL loop characteristic is adjusted in an optimum condition for the inner periphery, the pull-in range is narrower for the outer periphery, to take a long time for the lock-in. On the other hand, if the PLL loop characteristic is adjusted in an optimum condition of the outer periphery, the PLL loop gain is relatively higher during reproducing on the inner periphery, whereby there is a possibility that the clock jitter increases.
In the PLL circuit, if ω1 is changed without changing the ratio of ω0 to ω1 and ratio of ω2 to ω1 in the open-loop characteristic shown in FIG. 9, the pull-in characteristic of the PLL can be made comparable only with the time scale being changed, because the dumping coefficient is the same. FIG. 10 shows an idealistic PLL open-loop characteristic during a CAV operation. Graph (iv) and graph (v) in this figure represent the gain during reproducing on the outer periphery and on the inner periphery, respectively. As understood from FIG. 10, the characteristic wherein the PLL characteristic frequency is perfectly linearly shifted along the angular-frequency axis can be realized. Such a characteristic is desirable as the characteristic of the PLL circuit during the CAV reproduction. However, since the passive elements such as C and R determine the loop characteristic in an analog PLL, it is difficult to continuously change the values of these elements. In addition, since there is a temperature dependency and a variation with time, it is difficult to mass-produce PLLs having the same characteristics.
As to a conventional configuration example of the PLL that is scarcely affected by the temperature or variation with time, there is one described in Patent Publication-1. FIG. 11 shows the configuration of the PLL circuit described in Patent Publication-1. The PLL circuit 300 is a typical digital PLL, wherein a phase comparator 302 and a loop filter 303 are digitized. An A/D converter 301 performs A/D conversion of an input signal at the timing of a synchronizing clock output form a VCO 305. The phase comparator 302 compares the digital signal subjected to the A/D conversion against the synchronizing clock output from the VCO 305. The result of phase comparison is input to a D/A converter 304 via a loop filter 303, subjected to D/A conversion in the D/A converter 304, and then input to the VCO 305. The PLL circuit 300 includes a unit that controls the gain of the loop filter 303 in a special range wherein the PLL is subjected to pull-in. This allows the temperature characteristics and the variation with time of the filter section to be disregarded.
As to the correction technique of the PLL loop characteristic, there is a technique described in Patent Publication-2. FIG. 12 shows the configuration of the PLL circuit described in Patent Publication-2. In this PLL circuit 400, an input signal is input to a phase comparator 404, and at the same time input to a F/V converter 401. A/D conversion of an output of F/V converter 401 is performed in an A/D converter 402, whereby the channel frequency is detected in a CPU 403. The CPU 403 switches the characteristic of a loop filter (digital filter) 405 in accordance with the detected channel frequency, and at the same time controls the central frequency of a VCO 406. Control coefficients of the loop filter characteristic for the channel frequency are incorporated in the CPU 403 in the form of a table, whereby an optimum loop characteristic can be realized depending on the linear velocity.
Patent Publication-1: JP-1996-96516A
Patent Publication-2: JP-1989-277371A
Patent Publication-1 has an object to suppress the variation with time by the digitization, and in the configuration thereof, the digitized loop filter is operated with the synchronizing clock of the VCO, whereby the characteristic of the loop filter can be seamlessly changed depending on the oscillating frequency. However, the VCO characteristic cannot be changed, and accordingly, if the PLL characteristic is set optimum in, for example, the middle area for the CAV, and when the PLL is operated for the inner periphery, as shown in FIG. 13, ω0/ω1 assumes a lower value, whereas when the PLL is operated for the outer periphery, as shown in FIG. 14, ω0/ω1 assumes a higher value. More specifically, the dumping coefficient is changed. In this way, Patent Publication-1 cannot realize a seamless correction of the loop characteristic caused by the above change of linear velocity. The graphs in FIGS. 13 and 14 represent similarly to those in FIG. 9.
Although the PLL circuit in Patent Publication-1 includes a unit that controls the gain of the loop filter, this unit is provided for the purpose of achieving a higher-speed pull-in. Although there is a description in Patent Publication-1 that the switching of gain is conducted depending on the state of the input digital signal, a unit for detecting the frequency is not provided therein, whereby the PLL circuit in Patent Publication-1 cannot change the loop gain depending on the frequency. That is, it is impossible to seamlessly correct the gain depending on the CAV linear velocity.
In Patent Publication-2, the A/D converter 402 is needed for detecting the channel frequency, and the CPU 403 is needed for controlling the loop filter. For this reason, there is a problem in the PLL circuit 400 described in Patent Publication-2 that the circuit scale increases and power dissipation also increases. In Patent Publication-2, although the central frequency of VCO 406 is determined based on the output of F/V converter 401, it is needed for the F/V converter 401 to have a higher accuracy. This configuration of the F/V converter 401 cannot achieve a higher accuracy in this case.